In switching networks, specifically in ATM (Asynchronous Transfer Mode) switching networks, multiple switching elements are suitably connected to obtain networks with high switching capacity. Each element of the network constitutes a stage. Stages are preferably in odd number (3, 5, less frequently 7). Increasing the number of stages increases switching capacity but also network complexity.
Given the functional complexity required of each individual element and the high speed with which ATM streams have to be handled (typically 155 Mbit/s, 311 Mbit/s, 622 Mbit/s), from the construction point of view a compromise is sought between the switching capacity of the individual element and the required circuit complexity. According to the most common solutions available at present, the switching elements are 8.times.8 and 16.times.16 elements, i.e. each element switches 8/16 input streams onto an equal number of output streams. Those solutions represent an excellent compromise between complexity and switching capacity, taking also into account that, the more complex the elements are, the more difficult it is to ensure fully reliable operation and the lower are the yields when the related integrated circuits are manufactured.
The paper entitled "An ATM Switch Hardware Technologies Using Multichip Packaging" by Y. Doi et al., IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. 16, No. 1, February 1993, pp. 60 and fol., describes an ATM switching system in which multiple 4.times.4 elements, with shared buffer (i.e. with a service memory on the component shared by the various streams), are connected on a single substrate, to produce a 16.times.16 switching module. That type of connection solely aims to solve the problem of size due to the presence of multiple stages, and the final module is not managed as an individual stage. This clearly limits the overall capacity of a switching network using the modules, since the number of stages cannot be increased at will.